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FEATURES Single 8-Bit DAC 20-Pin SOIC/TSSOP Package +2.7 V to +5.5 V Operation Internal and External Reference Capability DAC Power-Down Function Parallel Interface On-Chip Output Buffer Rail-to-Rail Operation Low Power Operation 1.75 mA max @ 3.3 V Power-Down to 1 A max @ 25 C APPLICATIONS Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators
+2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC AD7801
FUNCTIONAL BLOCK DIAGRAM
D7 D0 INPUT REGISTER DAC REGISTER I DAC I/V VOUT
WR CS
CONTROL LOGIC
MUX
POWER-ON RESET
AD7801
PD CLR LDAC REFIN
/2
AGND
VDD
DGND
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7801 is a single, 8-bit, voltage out DAC that operates from a single +2.7 V to +5.5 V supply. Its on-chip precision output buffer allows the DAC output to swing rail to rail. The AD7801 has a parallel microprocessor and DSP compatible interface with high speed registers and double buffered interface logic. Data is loaded to the input register on the rising edge of CS or WR. Reference selection for the AD7801 can be either an internal reference derived from the VDD or an external reference applied at the REFIN pin. The output of the DAC can be cleared by using the asynchronous CLR input. The low power consumption of this part makes it ideally suited to portable battery operated equipment. The power consumption is less than 5 mW at 3.3 V, reducing to less than 3 W in power-down mode. The AD7801 is available in a 20-lead SOIC and a 20-lead TSSOP package.
1. Low Power, Single Supply operation. This part operates from a single +2.7 V to +5.5 V supply and consumes typically 5 mW at 3 V, making it ideal for battery powered applications. 2. The on-chip output buffer amplifier allows the output of the DAC to swing rail to rail with a settling time of typically 1.2 s. 3. Internal or external reference capability. 4. High speed parallel interface. 5. Power-down capability. When powered down the DAC consumes less than 1 A at 25C. 6. Packaged in 20-lead SOIC and TSSOP packages.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997
AD7801-SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution Relative Accuracy2 Differential Nonlinearity Zero-Code Error @ +25C Full-Scale Error Zero-Code Error Drift Gain Error3 DAC REFERENCE INPUT REFIN Input Range REFIN Input Impedance OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short Circuit Current Power Supply Rejection Ratio4 LOGIC INPUTS Input Current VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 3.3 V @ 25C TMIN to TMAX VDD = 5.5 V @ 25C TMIN to TMAX IDD (Power-Down) @ 25C TMIN to TMAX 8 1 1 3 -0.75 100 1
(VDD = +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 k All specifications TMIN to TMAX unless otherwise noted.)
Units Bits LSB max LSB max LSB typ LSB typ V/C typ % FSR typ V min/V max M typ V min/V max s max V/s typ nV-s typ nV-s typ typ mA typ %/% max A max V max V max V min V min pF max V min/V max mA max mA max mA max mA max A max A max VIH = VDD and VIL = GND See Figure 18 Conditions/Comments
to VDD and GND.
B Versions1
Guaranteed Monotonic All Zeros Loaded to DAC Register All Ones Loaded to DAC Register
1 to VDD/2 10 0 to VDD 2 7.5 1 0.2 40 14 0.0003 10 0.8 0.6 2.4 2.1 7 2.7/5.5 1.55 1.75 2.35 2.5 1 2
Typically 1.2 s 1 LSB Change Around Major Carry
VDD = 10%
VDD = +5 V VDD = +3 V VDD = +5 V VDD = +3 V
DAC Active and Excluding Load Current VIH = VDD and VIL = GND See Figure 6
NOTES 1 Temperature ranges are as follows: B Version: -40C to +105C 2 Relative Accuracy is calculated using a reduced code range of 15 to 245. 3 Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB. 4 Guaranteed by characterization at product release, not production tested. Specifications subject to change without notice.
t1
CS
t2
t3
WR
t4
D7-D0
t5
t6
LDAC
t7
t8
CLR
Figure 1. Timing Diagram for Parallel Data Write
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AD7801 TIMING CHARACTERISTICS1, 2
Parameter t1 t2 t3 t4 t5 t6 t7 t8 0 0 20 15 4.5 20 20 20
(VDD = +2.7 V to +5.5 V; GND = 0 V; Internal V DD/2 Reference. All specifications TMIN to TMAX unless otherwise noted.)
Units ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments Chip Select to Write Setup Time Chip Select to Write Hold Time Write Pulse Width Data Setup Time Data Hold Time Write to LDAC Setup Time LDAC Pulse Width CLR Pulse Width
Limit at TMIN, TMAX (B Version)
NOTES 1 Sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2. tr and tf should not exceed 1 s on any digital input. 2 See Figure 1.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
ORDERING GUIDE
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Reference Input Voltage to AGND . . . . -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . . -0.3 V to VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Commercial (B Version) . . . . . . . . . . . . . -40C to +105C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 700 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 143C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Model AD7801BR AD7801BRU
Temperature Range -40C to +105C -40C to +105C
Package Option* R-20 RU-20
*R = Small Outline; RU = Thin Shrink Small Outline.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7801 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD7801
PIN CONFIGURATION
(MSB) DB7 1 DB6 2 DB5 3 DB4 4 DB3 5 DB2 6 20 DGND 19 VOUT 18 NC 17 AGND
AD7801
16 REFIN
TOP VIEW 15 V DD (Not to Scale) 14 CLR DB1 7 (LSB) DB0 8 CS 9 WR 10 13 LDAC 12 PD 11 DGND
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No. 1-8 9 10 11 12 13 14 15 16 17 18 19 20
Mnemonic D7-D0 CS WR DGND PD LDAC CLR VDD REFIN AGND NC VOUT DGND
Function Parallel Data Inputs. 8-bit data is loaded to the input register of the AD7801 under the control of CS and WR. Chip Select. Active low logic input. Write Input. WR is an active low logic input used in conjunction with CS to write data to the input register. Digital Ground Active low input used to put the part into low power mode reducing current consumption to less than 1 A. Load DAC Logic Input. When this logic input is taken low the DAC output is updated with the contents of its DAC register. If LDAC is permanently tied low the DAC is updated on the rising edge of WR. Asynchronous Clear Input (Active Low). When this input is taken low the DAC register is loaded with all zeroes and the DAC output is cleared to zero volts. Power Supply Input. This part can be operated from +2.7 V to +5.5 V and should be decoupled to GND. External Reference Input. This can be used as the reference for the DAC. The range on this reference input is 1 V to VDD/2. If REFIN is tied directly to VDD the internal VDD/2 reference is selected. Analog Ground reference point and return point for all analog current on the part. No Connect Pin. Analog Output Voltage from the DAC. The output amplifier can swing rail to rail on its output. Digital Ground reference point and return point for all digital current on the part.
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Typical Performance Characteristics- AD7801
800 720 640 560 VOUT - mV 480 400 320 240 160 80 0 0 2 4 6 SINK CURRENT - mA 8 VDD = 5V AND 3V INTERNAL REFERENCE TA = +25 C DAC LOADED WITH 00HEX 5 4.92 4.84 4.76
3.5 3.25 3.0 2.75
VOUT - Volts
VOUT - Volts
4.68 4.6 4.52 4.44 4.36 4.28 4.2 0 VDD = 5V INTERNAL REFERENCE DAC REGISTER LOADED WITH FFHEX TA = +25C 2 4 6 SOURCE CURRENT - mA 8
2.5 2.25 2.0 1.75 1.5 1.25 1.0 0 VDD = 3V INTERNAL REFERENCE DAC REGISTER LOADED WITH FFHex TA = +25C 1 2 3 4 5 6 SOURCE CURRENT - mA 7 8
Figure 2. Output Sink Current Capability with VDD = 3 V and VDD = 5 V
0.5 0.45 0.4 VDD = 5V TA = +25 C
Figure 3. Output Source Current Capability with VDD = 5 V
4.0 3.5 3.0 INTERNAL REFERENCE LOGIC INPUTS = VDD OR GND DAC ACTIVE
Figure 4. Output Source Current Capability with VDD = 3 V
4.0 DAC ACTIVE INTERNAL REFERENCE TA = +25C 3.0 LOGIC INPUTS = VIH OR VIL
0.35
ERROR - LSBs
0.3 0.25 0.2 0.15
IDD - mA
2.0 1.5 1.0 0.5 0 -50 -25
VDD = 5.5V
IDD - mA
INL ERROR
2.5 2.0
DNL ERROR 0.1 0.05 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 REFERENCE VOLTAGE - Volts
VDD = 3.3V 1.0
LOGIC INPUTS = VDD OR GND
0 25 50 75 TEMPERATURE - C
100
125
0 2.5
3.0
3.5
4.0 4.5 VDD - Volts
5.0
5.5
Figure 5. Relative Accuracy vs. External Reference
10 5 0 ATTENUATION - dB -5 -10 -15 -20 -25 -30 -35 -40 1 VDD = 5V EXTERNAL SINEWAVE REFERENCE DAC REGISTER LOADED WITH FFHEX TA = +25C 10 100 1k FREQUENCY - Hz 10k
Figure 6. Typical Supply Current vs. Temperature
Figure 7. Typical Supply Current vs. Supply Voltage
WR 1
T
PD 2
2 VOUT VOUT
3
VDD = 3V INTERNAL VOLTAGE REFERENCE FULL SCALE CODE CHANGE 00H-FFH TA = +25C CH1 5V, CH2 1V, CH3 20mV TIME BASE = 200 ns/Div
1
VOUT AD7801 POWER-UP TIME VDD = 5V INTERNAL REFERENCE DAC IN POWER-DOWN INITIALLY CH1 = 2V/div, CH2 = 5V/Div, TIME BASE = 2 s/Div
Figure 8. Large Scale Signal Frequency Response
Figure 9. Full-Scale Settling Time
Figure 10. Exiting Power-Down (Full Power-Down)
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AD7801-Typical Performance Characteristics
10
T
9
ZERO CODE ERROR - LSB
VDD
8 7 6 5 4 3 2 1 VDD = 2.7 TO 5.5V DAC LOADED WITH ALL ZEROES INTERNAL REFERENCE
1
1
WR
2
T
VDD = 5V INTERNAL VOLTAGE REFERENCE 10 LSB STEP CHANGE TA = +25 C
VOUT
VOUT
2
CH1
5.00V CH2
5.00V M20.0ms CH1
0 -50
-25
0
25
50
75
100
125
CH1 5.00V, CH2 50.0mV, M 250ns
TEMPERATURE - C
Figure 11. Power-On--Reset
Figure 12. Zero Code Error vs. Temperature
Figure 13. Small-Scale Settling Time
0.5 0.4 0.3 VDD = 5V INTERNAL REFERENCE 5k 100pF LOAD LIMITED CODE RANGE (15-245) TA = +25C
0.5 0.4 0.3
0.5 0.4 0.3
INL ERROR - LSB
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 160 192 224 256 INPUT CODE (15 to 245)
INL ERROR - LSB
0.2
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
DNL ERROR - LSB
VDD = 5V INTERNAL REFERENCE
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 VDD = 5V INTERNAL REFERENCE
-0.5 -60 -40 -20
0 20 40 60 80 100 120 140 TEMPERATURE - C
-0.5 -60 -40 -20
0 20 40 60 80 100 120 140 TEMPERATURE - C
Figure 14. Integral Linearity Plot
Figure 15. Typical INL vs. Temperature
Figure 16. Typical DNL vs. Temperature
1.0
%
1000
VDD = 5V
POWER DOWN CURRENT - nA
900 800 700 600 500 400 300 200 100
VDD = 5V LOGIC INPUTS = VDD OR GND
0.8
INT REFERENCE ERROR -
0.6
0.4
0.2
0 -60 -40 -20
0 -50
-25
0 20 40 60 80 100 120 140 TEMPERATURE - C
0 25 50 75 TEMPERATURE - C
100
150
Figure 17. Typical Internal Reference Error vs. Temperature
Figure 18. Power-Down Current vs. Temperature
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AD7801
TERMINOLOGY Integral Nonlinearity
For the DAC, Relative Accuracy or End-Point nonlinearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A graphical representation of the transfer curve is shown in Figure 14.
Differential Nonlinearity
VDD 30k REFIN
REFERENCE AMPLIFIER
AD7801
11.7k CURRENT DAC 11.7k
I/V
VOUT
30k
Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.
Zero-Code Error
Figure 19. DAC Architecture
Zero-Code Error is the measured output voltage from VOUT of the DAC when zero code (all zeros) is loaded to the DAC latch. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in LSBs.
Gain Error
This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale value. It includes fullscale errors but not offset errors.
Digital-to-Analog Glitch Impulse
Digital-to-Analog Glitch Impulse is the impulse injected into the analog output when the digital inputs change state with the DAC selected and the LDAC used to update the DAC. It is normally specified as the area of the glitch in nV-secs and measured when the digital input code is changed by 1 LSB at the major carry transition.
Digital Feedthrough
The DAC output is internally buffered and has rail-to-rail output characteristics. The output amplifier is capable of driving a load of 100 pF and 10 k to both VDD and ground. The reference selection for the DAC can be either internally generated from VDD or externally applied through the REFIN pin. A comparator on the REFIN pin detects whether the required reference is the internally generated reference or the externally applied voltage to the REFIN pin. If REFIN is connected to VDD, the reference selected is the internally generated VDD/2 reference. When an externally applied voltage is more than one volt below VDD, the comparator selection switches to the externally applied voltage on the REFIN pin. The range on the external reference input is from 1.0 V to VDD/2 V. The output voltage from the DAC is given by:
N V O = 2V REF x 256
Digital Feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital inputs of the same DAC, but is measured when the DAC is not updated. It is specified in nV-secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa.
Power Supply Rejection Ratio (PSRR)
where VREF is the voltage applied to the external REFIN pin or VDD/2 when the internal reference is selected. N is the decimal equivalent of the code loaded to the DAC register and ranges from 0 to 255.
VDD
VTH PMOS COMPARATOR INT REF REFIN EXT REF INT REF MUX
This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power supply rejection ratio is quoted in terms of % change in output per % change in VDD for full-scale output of the DAC. VDD is varied 10%.
GENERAL DESCRIPTION D/A Section
The AD7801 is an 8-bit voltage output digital-to-analog converter. The architecture consists of a reference amplifier and a current source DAC followed by a current-to-voltage converter capable of generating rail-to-rail voltages on the output of the DAC. Figure 19 shows a block diagram of the basic DAC architecture.
SELECTED REFERENCE OUTPUT
Figure 20. Reference Selection Circuitry
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AD7801
Reference Automatic Update Mode
The AD7801 has the ability to use either an external reference applied through the REFIN pin or an internal reference generated from VDD. Figure 20 shows the reference input arrangement where either the internal VDD/2 or the externally applied reference can be selected. The internal reference is selected by tying the REFIN pin to VDD. If an external reference is to be used, this can be directly applied to the REFIN pin and if this is 1 V below VDD, the internal circuitry will select this externally applied reference as the reference source for the DAC.
Digital Interface
In this mode of operation the LDAC signal is permanently tied low. The state of the LDAC is sampled on the rising edge of WR. LDAC being low allows the DAC register to be automatically updated on the rising edge of WR. The output update occurs on the rising edge of WR. Figure 23 shows the timing associated with the automatic update mode of operation and also the status of the various registers during this frame.
CS WR D7-D0
The AD7801 contains a fast parallel interface allowing this DAC to interface to industry standard microprocessors, microcontrollers and DSP machines. There are two modes in which this parallel interface can be configured to update the DAC output. The synchronous update mode allows synchronous updating of the DAC output; the automatic update mode allows the DAC to be updated individually following a write cycle. Figure 21 shows the internal logic associated with the digital interface. The PON STRB signal is internally generated from the power-on reset circuitry and is low during the poweron reset phase of the power up procedure.
CLR CLR PON STRB CLEAR SET SLE DAC CONTROL LDAC LOGIC ENABLE CS WR MLE
LDAC = 0 I/P REG (MLE) DAC REG (SLE) HOLD TRACK TRACK HOLD TRACK
HOLD
VOUT
Figure 23. Timing and Register Arrangement for Automatic Update Mode
Synchronous Update Mode
LDAC
SLE
Figure 21. Logic Interface
The AD7801 has a double buffered interface, which allows for synchronous updating of the DAC output. Figure 22 shows a block diagram of the register arrangement within the AD7801.
DAC REGISTER 4 TO 15 DECODER
In this mode of operation the LDAC signal is used to update the DAC output to synchronize with other updates in the system. The state of the LDAC is sampled on the rising edge of WR. If LDAC is high, the automatic update mode is disabled and the DAC latch is updated at any time after the write by taking LDAC low. The output update occurs on the falling edge of LDAC. LDAC must be taken back high again before the next data transfer takes place. Figure 24 shows the timing associated with the synchronous update mode of operation and also the status of the various registers during this frame.
CS WR
4 DB7-DB0 INPUT REGISTER 8
15
15
DRIVERS
30 UPPER NIBBLE
D7-D0
LDAC I/P REG (MLE) HOLD TRACK HOLD
DAC REGISTER
4 TO 15 DECODER
4
15
15
DRIVERS
30
DAC REG (SLE) HOLD TRACK HOLD
LOWER NIBBLE
VOUT
MLE CS WR LDAC CLR
SLE
CONTROL LOGIC
Figure 24. Timing and Register Arrangement for Synchronous Update Mode
Figure 22. Register Arrangement
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AD7801
POWER-ON RESET
The AD7801 has a power-on reset circuit designed to allow output stability during power up. This circuit holds the DAC in a reset state until a write takes place to the DAC. In the reset state all zeros are latched into the input register of the DAC and the DAC register is in transparent mode thus the output of the DAC is held at ground potential until a write takes place to the DAC. The power-on reset circuitry generates a PON STRB signal which is a gating signal used within the logic to identify a power-on condition.
POWER-DOWN FEATURES
N V OUT = 2 xV REF 256
where: N is the decimal equivalent of the binary input code. N ranges from 0 to 255.
VREF is the voltage applied to the external REFIN pin when the external reference is selected and is VDD/2 if the internal reference is used.
Table I. Output Voltage for Selected Input Codes
The AD7801 has a power-down feature implemented by exercising the external PD pin. An active low signal puts the complete DAC into power-down mode. When in power-down, the current consumption of the device is reduced to less than 1 A max at +25C or 2 A max over temperature, making the device suitable for use in portable battery powered equipment. The internal reference resistors, the reference bias servo loop, the output amplifier and associated linear circuitry are all shut down when the power-down is activated. The output terminal sees a load of 23 k to GND when in power-down mode as shown in Figure 25. The contents of the data register are unaffected when in power-down mode. The device typically comes out of power-down in 13 s (see Figure 10).
11.7k VDD IDAC
Digital MSB . . . LSB 1111 1111 1111 1110 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000
2VREF
Analog Output
2x 2x 2x
255 xV REF V 256 254 xV REF V 256 129 xV REF V 256 127 xV REF V 256
V REF V 256
VREF V
2x
2x
0V
11.7k VREF
DAC OUTPUT VOLTAGE
Figure 25. Output Stage During Power-Down
Analog Outputs
VREF
The AD7801 contains a voltage output DAC with 8-bit resolution and rail-to-rail operation. The output buffer provides a gain of two at the output. Figures 2, 3 and 4 show the source and sink capabilities of the output amplifier. The slew rate of the output amplifier is typically 7.5 V/s and has a full-scale settling to eight bits with a 100 pF capacitive load in typically 1.2 s. The input coding to the DAC is straight binary. Table I shows the binary transfer function for the AD7801. Figure 26 shows the DAC transfer function for binary coding. Any DAC output voltage can be expressed as:
0
DAC INPUT CODE
00 01
7F 80 81
FE FF
Figure 26. DAC Transfer Function
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AD7801
Figure 27 shows a typical setup for the AD7801 when using its internal reference. The internal reference is selected by tying the REFIN pin to VDD. Internally in the reference section there is a reference detect circuit that will select the internal VDD/2 based on the voltage connected to the REFIN pin. If REFIN is within a threshold voltage of a PMOS device (approximately 1 V) of VDD the internal reference is selected. When the REFIN voltage is more than 1 V below VDD, the externally applied voltage at this pin is used as the reference for the DAC. The internal reference on the AD7801 is VDD/2, the output current to voltage converter within the AD7801 provides a gain of two. Thus the output range of the DAC is from 0 V to VDD, based on Table I.
VDD = 3V TO 5V
MICROPROCESSOR INTERFACING AD7801-ADSP-2101/ADSP-2103 Interface
Figure 29 shows an interface between the AD7801 and the ADSP2101/ADSP-2103. The fast interface timing associated with the AD7801 allows easy interface to the ADSP-2101/ADSP-2103. LDAC is permanently tied low in this circuit so the DAC output is updated on the rising edge of the WR signal. Data is loaded to the AD7801 input register using the following ADSP-21xx instruction. DM(DAC) = MR0 MR0 = ADSP-21xx MR0 Register. DAC = Decoded DAC Address.
DMA14
0.1 F 10 F
ADDRESS BUS
DMA0
AD7801*
REF IN CLR PD D7-D0 VDD CS WR LDAC VDD AGND DGND VOUT VOUT
DMS
EN
ADDR DECODE
CS LDAC WR DB7 DB0
AD7801
ADSP-2101*/ ADSP-2103*
WR
DATA BUS
CONTROL INPUTS
DMD15 DATA BUS DMD0
Figure 27. Typical Configuration Selecting the Internal Reference
*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
Figure 28 shows a typical setup for the AD7801 when using an external reference. The reference range for the AD7801 is from 1 V to VDD/2 V. Higher values of reference can be incorporated but will saturate the output at both the top and bottom end of the transfer function. There is a gain of two from input to output on the AD7801. Suitable references for 5 V operation are the AD780 and REF192. For 3 V operation a suitable external reference would be the AD589 a 1.23 V bandgap reference.
VDD = 3V TO 5V
Figure 29. AD7801-ADSP-2101/ADSP-2103 Interface
AD7801-TMS320C20 Interface
Figure 30 shows an interface between the AD7801 and the TMS320C20. Data is loaded to the AD7801 using the following instruction: OUT DAC, D DAC = Decoded DAC Address. D = Data Memory Address.
A15
0.1 F VIN
10 F
ADDRESS BUS
A0
EXT REF VOUT
GND 0.1 F
REF IN CLR PD
VDD
AGND DGND
IS EN
AD7801*
VOUT
ADDR DECODE CS LDAC WR R/W DB7 DB0 D15
AD7801
CS WR
VOUT
TMS320C20
STRB
AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 3V
D7-D0 VDD
LDAC
DATA BUS
CONTROL INPUTS
DATA BUS D0
Figure 28. Typical Configuration Using An External Reference
*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
Figure 30. AD7801-TMS320C20 Interface
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AD7801
In the circuit shown the LDAC is hardwired low thus the DAC output is updated on the rising edge of WR. Some applications may require synchronous updating of the DAC in the AD7801. In this case the LDAC signal can be driven from an external timer or can be controlled by the microprocessor. One option for synchronous updating is to decode the LDAC from the address bus so a write operation at this address will synchronously update the DAC output. A simple OR gate with one input driven from the decoded address and the second input from the WR signal will implement this function.
AD7801-8051/8088 Interface
VDD = 3V TO 5V R4 20k R3 10k VDD AGND DGND VOUT +5V AD820/ OP295 -5V R1 10k R2 20k DATA BUS CONTROL INPUTS 0.1 F 10 F
VIN
EXT REF VOUT
GND 0.1 F
REF IN CLR PD
5V
AD7801
CS WR LDAC
AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 3V
D7-D0 VDD
Figure 31 shows a serial interface between the AD7801 and the 8051/8088 processors.
Figure 32. Bipolar Operation Using the AD7801
A15 A8 ADDRESS BUS
Decoding Multiple AD7801s in a System
AD7801*
PSEN OR DEN
EN
ADDR DECODE
CS WR LDAC
WR
8051/8088*
ALE OCTAL LATCH
DB7 DB0
AD7 DATA BUS AD0
*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
The CS pin on the AD7801 can be used in applications to decode a number of DACs. In this application, all DACs in the system receive the same input data, but only the CS to one of the DACs will be active at any one time allowing access to one channel in the system. The 74HC139 is used as a two-to-four line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the Enable input on the 74HC139 should be brought to its inactive state while the Coded Address inputs are changing state. Figure 33 shows a diagram of a typical setup for decoding multiple AD7801 devices in a system. The built-in power-on reset circuit on the AD7801 ensures that the outputs of all DACs in the system power up with zero volts on their outputs.
Figure 31. AD7801-8051/8088 Interface
DATA BUS
AD7801
CS WR D0 D7 LDAC VOUT
APPLICATIONS Bipolar Operation Using the AD7801
WR
The AD7801 has been designed for unipolar operation but bipolar operation is possible using the circuit in Figure 32. The circuit shown is configured for an output voltage range of -5 V to +5 V. Rail-to-rail operation at the amplifier output is achievable by using an AD820 or OP295 as the output amplifier. The output voltage for any input code can be calculated as follows:
R4 2V REF D R4 V O = R2 1+ / R1+ R2 x -V REF R3 256 R3
VDD VCC 1Y0 1Y1 1Y2
1G ENABLE 1A 1B CODED ADDRESS
AD7801
CS WR D0 D7 LDAC VOUT
74HC139
1Y3 DGND
(
)
AD7801
CS WR D0 D7 LDAC VOUT
Where D is the decimal equivalent of the code loaded to the DAC and VREF is the reference voltage input. With VREF = 2.5 V, R1 = R3 = 10 k and R2 = R4 = 20 k and VDD = 5 V.
10D VO = -5 256
AD7801
CS WR D0 D7 LDAC VOUT
Figure 33. Decoding Multiple AD7801s
REV. 0
-11-
AD7801
AD7801 as a Digitally Programmable Indicator
VDD = 5V VSOURCE 0.1F 10F LOAD VIN
A digitally programmable upper limit detector using the DAC is shown in Figure 34. The upper limit for the test is loaded to the DAC, which in turn sets the limit for the CMP04. If a signal at the VIN input is not below the programmed value, an LED will indicate the Fail condition.
+5V 0.1 F 10 F VIN 1k FAIL 1k PASS
EXT REF VOUT
GND 0.1F
REF IN
VDD VOUT
+5V AD820/ OP295 2N3904/ BC107
AD7801
AGND DGND
AD780/ REF192 WITH VDD = 5V
4.7k
VDD
REFIN 470
AD7801
VOUT D7 D0 PASS/
Figure 35. Programmable Current Source
Coarse and Fine Adjustment using two AD7801s
DVDD
1/4 CMP-04
1/6 74HC05
DGND
AGND
Figure 34. Digitally Programmable Indicator
Programmable Current Source
Figure 35 shows the AD7801 used as the control element of a programmable current source. In this circuit the full-scale current is set to 1 mA. The output voltage from the DAC is applied across the current setting resistor of 4.7 k in series with the full-scale setting resistor of 470 . Suitable transistors to place in the feedback loop of the amplifier include the BC107 and the 2N3904, which enable the current source to operate from a minimum VSOURCE of 6 V. The operating range is determined by the operating characteristics of the transistor. Suitable amplifiers include the AD820 and the OP295, both of which have rail-to-rail operation on their outputs. The current for any digital input code can be calculated as follows:
I=
The two DACs can be paired together to form a coarse and fine adjustment function for a setpoint as shown in Figure 36. In this circuit, the first DAC is used to provide the coarse adjustment and the second DAC is used to provide the fine adjustment. Varying the ratio of R1 and R2 will vary the relative effect of the coarse and fine tune elements in the circuit. For the resistor values shown, the second DAC has a resolution of 148 V giving a fine tune range of 38 mV (approximately 2 LSB) for operation with a VDD of 5 V and a reference of 2.5 V. The amplifier shown allows a rail-to-rail output voltage to be achieved on the output. A typical application for the circuit would be in a setpoint controller.
VDD = 5V R3 51.2k 0.1F 10F +5V VIN VDD VOUT R1 390 AD820/ OP295 VO R4 390
EXT REF VOUT
GND 0.1F
REF IN
AD7801
AGND DGND
(256 (5 k))
(2 V REF D )
AD780/ REF192 WITH VDD = 5V OR AD589 WITH VDD = 3V
REF IN 0.1F
VDD VOUT R2 51.2k
AD7801
AGND DGND
Figure 36. Coarse and Fine Adjustment
-12-
REV. 0
AD7801
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD7801 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD7801 is in a system where multiple devices require an AGND to DGND connection, the connection should be made at one point only, a star ground point which should be established as closely as possible to the AD7801. The AD7801 should have ample supply bypassing of 10 F in parallel with 0.1 F located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitors should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
The power supply lines of the AD7801 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effect of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side.
REV. 0
-13-
AD7801
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Wide Body SOIC (R-20)
0.5118 (13.00) 0.4961 (12.60)
20 11
1
10
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
8 0.0500 0.0192 (0.49) 0 (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
20-Lead TSSOP (RU-20)
0.260 (6.60) 0.252 (6.40)
20
11
0.177 (4.50) 0.169 (4.30)
1
10
0.006 (0.15) 0.002 (0.05)
PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50) 0.246 (6.25)
SEATING PLANE
8 0
0.028 (0.70) 0.020 (0.50)
-14-
REV. 0
-15-
-16-
C2995-12-4/97
PRINTED IN U.S.A.

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